Generally, modern processors employ varying methods of clock gating to decrease power consumption. Processors use electrical signals called clock signals to advance operations within the system by clocking synchronous elements. The system typically sends a clock signal at regular intervals, and the signal instructs the synchronous elements to operate. Clock gating adds logic elements to a system design to disable the clock to inactive elements in the system. In traditional system operation, the clock regularly instructs the synchronous elements to operate. Each time a particular clock operates synchronous elements, those synchronous elements controlled by the particular clock draw operating power. Those skilled in the art refer to power consumed in response to clock signals as dynamic power. Even when the synchronous elements are not performing a function, the synchronous elements continue to consume dynamic power every time the system sends a clock signal. Clock gating inserts logic into the system in order to control which synchronous elements the clock operates. When particular elements within the system are inactive, the logic gates prevent the element from receiving the clock signal. Consequently, the element does not operate and does not draw dynamic power.
While prior art clock gating methods reduce the dynamic power load from a system, the inactive elements continue to draw power even when isolated from the clock. The continued power draw originates from the need to maintain the elements in a ready state for the next operational clock period. Persons skilled in the art refer to the continued power draw as leakage power, or leakage power loss. Clock gating on its own does not reduce leakage loss. Leakage loss poses a serious problem. As devices continue to decrease in size, lower voltage supplies are used to operate a system, necessitating processor systems that consume less power. Additionally, as battery operated applications in processors increase, persons skilled in the art continue to seek methods that increase the efficient use of power.
One prior art method designed to reduce leakage power loss involved creating a sleep mode process. A system utilizing a sleep mode process will remove power from all elements of the system outside of those that are needed to restore the system to its operating state. However, sleep mode incurs a time penalty, or wake up penalty, in that it takes a significant amount of time, or a significant number of clock periods to restore power to those elements that have had power removed from them. Therefore, there is a need for a system and/or method for improved power reduction in modern processors that addresses at least some of the problems and disadvantages associated with conventional methods.